set_app_var auto_wire_load_selection false
set_wire_load_mode top

set_max_area 0
set_max_fanout 32 [current_design]
set_max_capacitance 10 [current_design]
set_max_transition 0.4 [current_design]

create_clock -period 40.000 -name clk [get_ports clk_pad]
set_clock_uncertainty -setup 12.000 [get_clocks clk]

set_input_delay -clock clk -max 25 [get_ports * -filter "direction == in"]
set_input_delay -clock clk -min 0 [get_ports * -filter "direction == in"]
set_output_delay -clock clk -max 25 [get_ports * -filter "direction == out"]
set_output_delay -clock clk -min 0 [get_ports * -filter "direction == out"]


set_ideal_network -no_propagate [get_ports clk_pad]
set_ideal_network -no_propagate [get_nets clk]
set_ideal_network -no_propagate [get_nets rstn]
